MAX1499ECJ+【PDF 2/33 页】IC ADC 3 1/2DIG W/LED DVR 32TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录2009

1页 [2页]3页 4页 5页 6页

MAX1497/MAX1499

3.5- and 4.5-Digit, Single-Chip ADCs with LED

Drivers and C Interface

______________________________________________________________________________________

Pin Description

PIN

MAX1497

MAX1499

NAME

FUNCTION

131

VNEG

-2.5V Charge-Pump Voltage-Output. Connect a 0.1F capacitor to GND.

232

REF-

Negative Reference Voltage Input. For internal reference operation, connect REF- to

GND. For external reference operation, bypass REF- to GND with a 0.1F capacitor and

set VREF- from -2.2V to +2.2V, provided VREF+ > VREF-.

REF+

Positive Reference Voltage Input. For internal reference operation, connect a 4.7F

capacitor from REF+ to GND. For external reference operation, bypass REF+ to GND

with a 0.1F capacitor and set VREF+ from -2.2V to +2.2V, provided VREF+ > VREF-.

AIN+

Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to GND

with a 0.1F or greater capacitor.

AIN-

Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to

GND with a 0.1F or greater capacitor.

ISET

Segment Current Controller. Connect to ground through a resistor to set the segment

current. See Table 6 for segment current selection.

GND

Ground

8—

VDD

Analog and Digital Circuit Supply Voltage. Connect VDD to a +2.7V to +5.25V power

supply. Bypass VDD to GND with a 0.1F and a 4.7F capacitor.

CLK

External Clock Input. When the EXTCLK register bit is set to one, CLK is the master clock

input (frequency = 4.9152MHz) for the modulator and the filter. When the EXTCLK

(MAX1499) or VDD (MAX1497) when the internal oscillator is used.

EOC

Active-Low End-of-Conversion Logic Output. A logic low at EOC indicates that a new

ADC result is available in the ADC result register.

Active-Low Chip Select Input. Forcing CS low activates the serial interface.

DIN

Serial Data Input. Data present at DIN is shifted into the internal registers in response to

a rising edge at SCLK when CS is low.

SCLK

Serial Clock Input. Apply an external clock to SCLK to facilitate communication through

the serial bus. SCLK may idle high or low.

DOUT

Serial Data Output. DOUT presets serial data in response to register queries. Data shifts

out on the falling edge of SCLK. DOUT goes high impedance when CS is high.

DIG0

Digit 0 Driver

DIG1

Digit 1 Driver

GLED

Ground for LED-Display Segment Driver

DIG2

Digit 2 Driver

DIG3

Digit 3 Driver

SEGA

Segment A Driver

SEGB

Segment B Driver

SEGC

Segment C Driver

SEGD

Segment D Driver

SEGE

Segment E Driver

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式